Nonvolatile semiconductor memory circuits
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United States of America Patent
Stats
-
Jul 27, 1982
Grant Date -
N/A
app pub date -
Oct 31, 1980
filing date -
Nov 12, 1979
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An NMOS non-volatile latch having N-channel drivers Q.sub.1 and Q.sub.2 and variable threshold N-channel FATMOS transistors Q.sub.3 and Q.sub.4 as depletion loads. The control gate of each FATMOS transistor is coupled to its own node (X.sub.1 or X.sub.2) so as to operate in depletion, whereas to obtain the correct voltage stresses the tunnels of the FATMOS floating gates are cross-coupled to the opposite latch nodes.
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