Importance

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Abstract

A decoder in which the decoding of N input variables to produce 2.sup.N unique outputs is carried out in steps, and in which some of the signals to be decoded also function to power part of the decoding circuitry. First, X of the N variables are decoded separately, as a group, to produce 2.sup.X unique outputs while the remaining N-X variables are also separately decoded, as a group, to produce 2.sup.(N-X) unique outputs, where N and X are positive integers and X is less than N. Then, the outputs of the two groups are logically combined by means of 2.sup.N decoding buffer gates to produce 2.sup.N unique outputs. Each one of the 2.sup.X unique outputs is applied to the signal input terminals of 2.sup.(N-X) different ones of the 2.sup.N buffer gates and each one of the 2.sup.(N-X) unique outputs is used to power 2.sup.X different ones of the 2.sup.N buffer gates to produce 2.sup.N unique outputs of the N input variables, at the outputs of the buffer gates.

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First Claim