Partitionable parallel processor

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United States of America Patent

PATENT NO 4344134
SERIAL NO

06164097

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Abstract

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In a parallel processing array wherein each processor therein issues a ready signal to signify that it is ready to begin a parallel processing task and initiates the task upon receipt of an initiate signal the parallel processing array is rendered partitionable into parallel processing subarrays by a control node tree having a plurality of control nodes connected to the plurality of processors and in decreasing levels to each other in a tree-like fashion down to a single root node. Each node is controlled to function as a non-root wherein it receives a ready signal from its processor side and passes it along toward the single root node or as a root node whereupon receiving a ready signal it issues back an initiate signal toward the plurality of processors.

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Patent Owner(s)

Patent OwnerAddress
UNISYS CORPORATION801 LAKEVIEW DRIVE SUITE 100 BLUE BELL PA 19422

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Barnes, George H Wayne, PA 5 270

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