Importance

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Abstract

A buffer circuit (10) receives an enable signal to drive power transfer transistors (12,14) which supply power to circuit elements in a semiconductor memory. When an enable signal is driven to a high state the gate terminals of the power transfer transistors (12,14) will be driven positive thereby rendering the transistors conductive. When the enable signal transitions to a low voltage state first and second clock signals (.phi.C1 and .phi.C2) are generated. The action of the clock signals serves to pull a node (20) to one voltage threshold below the reference V.sub.ss. A second node (64) is driven to two thresholds below the reference of V.sub.ss. The second node (64) connected to the gate terminal of the power transfer transistors (12,14) to affirmatively hold the power transfer transistors (12,14) in a nonconductive state to essentially block the transfer of any current through these transistors to the circuit elements of the semiconductor memory thereby eliminating any power loss due to current leakage through the power transfer transistors (12,14).

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First Claim