Importance

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Abstract

A digital circuit receives symmetrical clock pulses of frequency F and outputs symmetrical pulses of frequency 1/3 F. A divide by one and one-half circuit clocks a divide by two flip-flop resulting in a symmetrical divide by three output. The divide by one and one-half circuit includes a pair of JK flip-flops and logic gates which receive clock pulses of frequency F and generate a plurality of staggered signal streams with nonsymmetrical pulses of frequency 1/3 F and a duty cycle of substantially 33%. The input clock pulses are gated against two of these streams to provide an output pulse during the first half of the duty portion of a cycle of one of the streams, and another output pulse during the second half of the duty portion of a cycle of the other stream, to provide an output frequency of 2/3 F which then clocks the divide by two flip-flop.

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First Claim