Memory board automatically assigned its address range by its position

United States of America Patent

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Oct 12, 1982
Grant Date
N/A
app pub date
Feb 11, 1980
filing date
Feb 16, 1979

priority date (Note)
Expired

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Abstract

A subtractor circuit subtracts start address information supplied from address information to produce a logical address. An adder circuit adds the start address information to memory capacity information to form the start address of the succeeding memory board. When 0.ltoreq.output information from the subtraction circuit

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Patent Owner(s)

Patent Owner	Address
TOKYO SHIBAURA DENKI KABUSHIKI KAISHA	72 HORIKAWA-CHO SAIWAI-KU KASWASAKI-SHI KANAGAWA-KEN

International Classification(s)

G11C:STATIC STORES

[Classification Symbol]

[Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Sato, Fumitaka	Ome, JP	79	1610

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Memory board automatically assigned its address range by its position

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United States of America Patent

06120469

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PATENT NO	4354258
SERIAL NO	06120469
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06120469

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