Programmable sequential logic array mechanism
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United States of America Patent
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-
Nov 2, 1982
Grant Date -
N/A
app pub date -
Dec 26, 1979
filing date -
Dec 26, 1979
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A programmable sequential logic array mechanism is provided for performing logical operations and solving logical equations. The mechanism includes a search array subsystem for receiving a plurality of binary input signals. The search array subsystem includes an addressable storage array for supplying input control words for testing for different input signal conditions. The sequential logic array mechanism also includes a read array subsystem for producing a plurality of binary output signals. This read array subsystem includes an addressable storage array for supplying output signal control words. The results of the tests performed by the search array subsystem are used to select which ones of the output signal control words are allowed to establish or change the read array output signals.
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