Double redundant processor
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United States of America Patent
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Nov 9, 1982
Issued Date -
N/A
app pub date -
Apr 12, 1979
filing date -
Mar 25, 1977
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A double redundant processor including first and second master processors for processing data, control and address signals in a data processing system. The first master processor is in an active state for processing the signals and the second master processor is in a standby state for processing the signals. The first and second master processors include first and second subprocessors for simultaneously processing the data, control and address signals, a comparator connected to compare the signals from the first and second subprocessors, thereby generating a comparison error signal if a disagreement exists, and an alarm monitor responsive to the error signal for inactivating the active master processor and activating the standby master processor.
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