Importance

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Abstract

A register circuit for processing information in accordance with a given instruction set or set of transformation comprises N registers each having an input and an output and provided in a sequence R.sub.1, R.sub.2, R.sub.3, . . . R.sub.N, each register having n digits where N and n are integers. The output of the first register R.sub.1 is connected to a first bus while its input is connected to a second bus. All of the other registers R.sub.2, R.sub.3, . . . R.sub.N have their inputs connected to the first bus and their outputs to the second bus by respective strobe circuits. The strobe circuits of each of the buses R.sub.3 . . . R.sub.N are connected to respective control inputs a.sub.3 . . . a.sub.N. Additional control inputs a.sub.1 and a.sub.2 are connected to an OR-gate whose output is applied to the input strobe circuit of register R.sub.2 while the input a.sub.2 is also applied directly to the output strobe circuit of register R.sub. 2. This allows transfer of the contents of the first register to the second upon the application of a signal to the input a.sub.1 and parallel transfer between all the registers by the appropriate control inputs.

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First Claim