Importance

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Abstract

A flexible, modular communications processor is disclosed comprised of a plurality of microprocessors. A demand assigned bus is provided to couple the microprocessors through an arbitrator to an information storage and retrieval device. Each of the microprocessors comprises a conventional integrated circuit microprocessor, associated local memory, transmitters and receivers for coupling information to and from the bus and bus access circuitry, cooperating with the arbitrator to allocate the bus resource. Communication input/output is handled by a plurality of microprocessors configured as line processors, each coupled to its associated interface switch, which, in turn, is coupled to modems or other input/output devices. A background or executive microprocessor is included to manage system configuration and react to failures. The common bus actually comprises a pair of buses and modularity is provided by allowing the number of line processors to be changed by inserting or deleting circuit cards without affecting the operation of other line processors. The communications processor may be redundantly configured by providing an additional arbitrator and additional executive or background processor and information storage and retrieval device such that all common equipment is redundant. On the other hand, the processor can be configured for load sharing wherein a plurality of line processors and one of the executive or background processors operate on one bus under control of an arbitrator operating to and from one of the information storage and retrieval devices, while the other executive or background processor cooperates with a different group of line processors over the other bus under control of the other arbitrator to and from the other information storage and retrieval device.

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First Claim