Importance

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Abstract

A modular terminal system (10) employs a CPU module (22) connected via a bus (20) to at least one slave module (24, 26, 28, 32, 36). An error condition is detected if a slave module fails to respond to a command by generating an operation acknowledge signal within a predetermined period of time associated with the time required for the slave module to execute the command. A memory mapping device (74) is utilized to decode CPU address signals and generate related signals on a greater number of output lines coupled to the system bus thereby increasing the number of addressable locations otherwise accessible by the CPU. Improved prioritized bus communication is provided by way of a vectored interrupt scheme (210) in which a priority line (212) is coupled in a daisy chain fashion to other slave modules in the system. In the preferred embodiment the system employs distributed CPU modules (22, 24) employing an interprocessor interrupt technique utilizing a pair of commonly accessible storage devices (300, 302). One of the processors may be used as an emulator and a programmable logic array (406) is advantageously utilized in the emulator processor.

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First Claim