Memory controller with queue control apparatus
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United States of America Patent
Stats
-
Dec 28, 1982
Grant Date -
N/A
app pub date -
Oct 31, 1980
filing date -
Oct 31, 1980
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the controller to operate in a corresponding number of different modes. The controller includes queue timing and control apparatus which couples to the modules and to the queue circuits for minimizing conflicts between the types of requests and the internal operations required to be performed by the controller.
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