Importance

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Abstract

An aligner is used in a digital telecommunications switching system for correcting the drift between the exchange clocking system and the incoming digital line terminated on the digital line termination units DLT. Typically aligners consists of so-called 'elastic-lengthed' buffers having two frames worth of storage arranged such that the line information is written into one 'frame area' while the time switch is fed from the other 'frame area' and vice versa for each successive frame. Such an arrangement has severe limitations from a fault finding point of view. The aligner of the invention consists of a 'single chip' containing a set of five half frame serial shift registers together with read and write address counters and associated logic to ensure that separate 'read' and 'write' shift registers are maintained. The use of five half frame shift registers through which the serially received data is passed allows the sync channel (time slot zero) to be monitored which ensures that the aligner is functioning correctly because the sync channel is fed through all the locations of the aligner. The sub-division of the total store into odd numbers allows each register selection to be checked periodically for the appearance and non-appearance of the synchronization pattern. In addition the checkable channel pattern is arranged to be the last entry written to each register before the counter moves to a new register, hence, the counter itself is checked across its full range.

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First Claim