Circuit for decreasing the effect of parasitic capacitances in field effect transistors used in coupling networks
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United States of America Patent
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Feb 1, 1983
Grant Date -
N/A
app pub date -
Apr 30, 1980
filing date -
May 4, 1979
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The loading due to parasitic capacitances on the input amplifiers of a coupling network which connects a plurality of input lines each including one of the input amplifiers selectively to a plurality of output lines and which uses field effect transistors as coupling elements is improved by the use of compensation amplifiers. Specifically, the source of each FET is connected to one of the input lines, while the drain is connected to an output line. Each compensation amplifier has an input connected to one output line and an output connected to the bulk terminal of each FET having a drain connected to the particular output line. Since the gain of the compensation amplifiers is unity, the voltage applied to the bulk terminals is equal to the output voltage shifted by the drain-bulk voltage.
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