Importance

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Abstract

A dynamic address translation system for use in a channel or sub-system adapter, wherein the main memory of a system is used in common with a central processing unit. The system provides registers for storing a copy of an entry within the address translation table in the main memory and a bit which indicates the validity of such a copy, and when the central processing unit has issued an instruction for updating the entry within said address translation table or an instruction to alter said entry, the bit which indicates the validity of the contents of said register, is changed so as to indicate invalidity of the associated register contents. It is unnecessary in this system to fix the page in the main memory prior to execution of channel programs.

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First Claim