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Abstract

Apparatus which detects and corrects both transient and single bit memory read errors while selectively logging only solid (that is, hardware-related) single bit memory read errors. Each of a plurality of memory modules directly transmits uncorrected memory data to a processor memory control while also providing for automatic local restoring of corrected data back into the memory address which produced the single bit error. The processor memory control provides its own error detection and correction employing syndrome generating and decoding circuitry which detects both multiple and single bit errors. Multiple bit errors are not corrected, but merely brought to the attention of the processor. Single bit errors are corrected, but only those which are found to most likely be solid errors are logged. A solid single bit error is recognized by detecting when two single bit errors having the same memory address occur consecutively.

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First Claim