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Abstract

A microprocessor-based circuit for interfacing between a plurality of serial data terminals and an external parallel data operating system. The interface circuit includes an asynchronous receiver-transmitter, which converts serial data to parallel data and converts parallel data to serial data. The interface circuit multiplexes received serial data from the terminals and couples that serial data to the receiver-transmitter. The microprocessor in the interface circuit further controls the transfer of this now-parallel data to the external parallel data operating system. The microprocessor also controls the transfer of parallel data from the parallel data operating system, which is converted to serial data by the asynchronous receiver-transmitter, demultiplexed by the interface circuit and transmitted to the terminals. Both the transmission and the reception of serial data is coordinated by the microprocessor, which also controls the receiver-transmitter and a set of registers connected to the operating system on a parallel data bus.

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First Claim