Importance

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Abstract

Logic circuit hardware is provided for dividing a binary fraction divisor into a smaller binary fraction dividend to provide a binary fraction quotient. Initially, the divisor is stored in a storage register with its sign in the highest order bit position and remains unchanged during the division operation. Initially, the dividend is stored in a dividend shift register and is shifted left one bit before being applied to a parallel adder to perform a partial divide operation. A clock signal is provided to time the division operations, wherein, the stored dividend is added to the stored divisor in a parallel binary adder. When the highest order or sign bit of the adder is positive, the sum of the dividend and the divisor are stored in the dividend register and a binary one is stored in a quotient register. When the highest order or sign bit of the adder is negative, the dividend register is shifted left and a binary zero is filled in the quotient register. Control means, including clock means, are connected logically to effect the division operation and data transfer without software implementation.

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First Claim