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Abstract

A circuit (10) and method for converting a circuit input frequency signal (f.sub.i) to a circuit output frequency signal (f.sub.o) comprising a phase-locked loop (22) for multiplying the input frequency signal (f.sub.i) by a value M to produce a multiple frequency signal (f.sub.i M), and a presettable divider for dividing the frequency signal (f.sub.i M) by a settable value N to produce the output frequency signal (f.sub.o). The circuit (10) and method are used to determine engine speed by converting the signal (f.sub.i) to the signal (f.sub.o) which can be used with a counter having a one second time base to determine such speed. The conversion occurs in the frequency domain and follows smoothly any change in engine speed.

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First Claim