System for reducing access time to plural memory modules using five present-fetch and one prefetch address registers

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United States of America Patent

PATENT NO 4384342
SERIAL NO

06201396

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Abstract

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A lookahead (guessahead) prefetching technique is used to reduce the average access time, for accessing memory modules when program addresses are modified into effective addresses for addressing the modules. A first memory address register stores the column address and module designation portions of the current effective address, a second memory address register stores the row address portion of the current effective address, and a third memory address register stores the module designation portion of the prior effective address. Since the same module is frequently accessed many times in succession, the average access time is reduced by starting an access based upon the contents of the second and third memory address registers without waiting until the column address and module designation portions of the current effective address are available for storage in the first memory address register. The access is completed, after the column address and module designation portions of the current effective address are determined, if a comparator which is connected to the first and third memory address registers confirms that the same memory module is being successively accessed. If not, the modules are accessed again based upon the contents of the first and second memory address modules.

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Patent Owner(s)

Patent OwnerAddress
PANAFACOM LIMITED A CORP OF JAPAN534 FUKAMI YAMATO-SHI KANAGAWA 242

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Imura, Takao Yamato, JP 1 17
Joda, Yoshihiro Yokohama, JP 1 17
Koyanagi, Shigeru Yokohama, JP 2 19

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