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Abstract

A fully distributed computing system comprises several processors, each having an arbitrarily long unique logical address. A bidirectional bus connects each of the processors and is used for communicating information between and among processors, and for resolving requests from a competing set of processors desiring access to the bus for subsequent communication with another processor. Resolving apparatus, comprising pan-processor control lines and a resolution member within each processor, awards bus access to that competing processor having the lowest logical address. All control lines within the resolving apparatus are bidirectional; as a result, the system 'fails soft,' i.e., there is no single point of failure in the system; one of the processors can fail without disrupting the operation of the remainder of the system. Each processor's resolution member comprises one or more resolve elements, which can be single-bit, dual-bit, or multi-bit resolve elements. As an example, a single-bit resolve element is a circuit for determining whether a binary test bit representing one bit position of the logical address for that processor is at least as low as the lowest bit from a set of other bits representing the same bit position of the logical address of each of the other competing processors. For resolve elements other than single-bit, binary addresses are converted into unitary representation, thus removing ambiguities from the system, enabling the instantaneous identification of all active addresses on the bus, and the unambiguous detection of the identity of a failed processor of the competing processors.

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First Claim