System and method for LSI circuit analysis
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United States of America Patent
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May 31, 1983
Grant Date -
N/A
app pub date -
Dec 31, 1979
filing date -
Dec 31, 1979
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system and method for analysis of circuits which include a large number of circuit elements. Blocks of circuitry which define logical circuit functions such as gates and latches are set up as macromodels. Each macromodel need be represented in its full detail only once. Means are provided to recognize latency, or quiescence, of macromodels so that time may be saved in the circuit analysis when a macromodel is latent.
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