Integrated circuit device connection process
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United States of America Patent
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-
Jul 12, 1983
Grant Date -
N/A
app pub date -
Jul 27, 1981
filing date -
Jul 27, 1981
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method for forming electrical interconnections in an integrated circuit which involves forming an insulating layer on the silicon chip on the lower of two conductive layers to be interconnected, opening a window in the insulating layer, filling the window with a metallic plug by a lift-off technique, and then forming an interconnection pattern extending over the layer and contacting the plug.
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