Power MOS transistor with a plurality of longitudinal grooves to increase channel conducting area
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United States of America Patent
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-
Jul 12, 1983
Issued Date -
N/A
app pub date -
Jun 16, 1980
filing date -
Jun 16, 1980
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor device providing improved utilization of semiconductor surface area by enhancing the current carrying capability per unit area. The improvement arises from contouring the surface in the conductive channel region of the device so that the current carrying channel is wider than the plane surface that it occupies. This morphology may be achieved by forming troughs having optional rectangular, 'U', or 'V' shapes; the troughs run parallel to the conductive channel current flow. The improvement is especially useful for MOS and power MOS transistors, and is applicable to DMOS transistors as well as conventional MOS transistors.
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