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Abstract

A programmable device for signal processing applications in which short loops of digital data are processed repetitively and in parallel. The device consist of five independently programmable subsystems whose functions are able to operate simultaneously. The apparatus is intended for use in a connection with a digital multiplier device and a digital memory device for such signal processing applications as fast Fourier transforms and time domain filtering in real time or near real time. The five parallel functions are 1. to move data in and out of an external memory device between selected registers; 2. to move data in and out of an external multiplier between selected registers and an arithmetic logic unit (ALU); 3. to move data from the output of a multiplier to selected registers and to the ALU; 4. to propagate data selectively through a chain of registers, the chain being of preselectable length; and 5. to perform selected arithmetic and logic operations. The device is provided with an instruction set capable of completely defining any of the five simultaneously allowable functions. The device structure is modular to permit expansion of data word length at the ALU. Internally generated control bit signals are capable of explicitly forcing a carry or inhibiting a carry, thereby to permit independent parallel operation or extended word length operation under program control. The entire apparatus is intended to be embodied as an integrated circuit in a single chip of semiconductor material.

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