Importance

Loading Importance Indicators...

Abstract

An error-correcting system is disclosed, which is located between a main memory and a central processing unit. The system includes a relief bit memory, an ECC or Error Correction Code logic circuit, a switching circuit and a correction controlling circuit. The ECC logic circuit detects the occurrence of a soft error and a hard error. When a hard error occurs in the memory, the defective memory cell thereof is switched to the relief bit memory. Accordingly, data to be written into the main memory or the relief bit memory is switched by means of the switching circuit. Similarly, data to be read from the main memory or the relief bit memory is also switched by the switching circuit. The data to be stored in the relief bit memory is validated by means of the ECC logic circuit and the switching circuit. Further, the (n+1)-bit soft and hard errors are reduced to n-bit soft and hard errors by means of the ECC logic circuit and the switching circuit.

Loading the Abstract Image...

First Claim