Fabrication method for high power MOS device
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United States of America Patent
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Aug 16, 1983
Issued Date -
N/A
app pub date -
Sep 9, 1981
filing date -
Apr 15, 1977
priority date (Note) -
Expired
status (Latency Note)
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Abstract
This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device. Another embodiment discloses the use of a self-aligned metal contact to the source or drain region of the VMOS device between adjacent V groov
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