Non-volatile, electrically erasable and reprogrammable memory element
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United States of America Patent
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Aug 16, 1983
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N/A
app pub date -
Aug 22, 1980
filing date -
Aug 24, 1979
priority date (Note) -
Expired
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Abstract
The invention relates to non-volatile electrically erasable and reprogrammable memories produced by CMOS technology. According to the invention, each memory element comprises only a single p-channel transistor having a polycrystalline silicon floating gate capacitively coupled to a control electrode. The thicknesses of injection oxide and gate oxide are such that the element can be programmed by avalanche of the drain-substrate junction and erased by field emission of electrons from the floating gate towards the substrate. All the voltages required can be generated on the circuit of the memory from a battery voltage of 1.5 volts.
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