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Abstract

A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. Each instruction is executed in a sequence of microstates which are generated by selecting an entry point for the first address in a control ROM then continuing with a series of jumps and/or further entry points determined by the instruction and by the current state of the microprocessor. Improved circuitry is provided for selecting the entry point using a minimum of space on the chip by detecting the position of the leading 1 bit. Thus an instruction set can be used in which different groups of instructions have different numbers of leading zero bits.

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First Claim