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Abstract

A state clock provides a bilevel signal of frequency which is an even multiple of the frequency of an incoming digital signal. A plurality of latches are responsive to the state signal. The outputs of the latches go to corresponding inputs of a memory array, the outputs of which are a plurality of terminals equal in number to the binary bits of a word stored in each address of the memory array. One of the output leads of the memory array passes through one of the state latches and to the output circuit. The other outputs go to the state latches where they are stored temporarily. The state latches are set on the rising transition of the state clock, while an input signal latch is set on the falling transition of the state clock. In this way at each cycle of the state clock the phase of the output signal is compared to that of the input signal; and if it is different, a corresponding output word of the memory array is fed back to the input to select the new output word and the new output signal, the phase of which will be closer to the phase of the input signal.

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First Claim