Semiconductor memory

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United States of America Patent

PATENT NO 4408304
SERIAL NO

06260297

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A semiconductor memory is provided with a hook structure composed of first to fourth regions and is capable of non-destructive readout. The third and fourth regions of the hook structure are both made floating and each form one of main electrode regions of each of a write and/or refresh transistor and a readout transistor. Carriers which are injected from the other main electrode region of the write transistor are stored as excess majority carriers in the third region and majority carriers of the fourth region flow out therefrom into the first region via the third and second regions, in consequence of which the fourth region lacks in the majority carrier and voltages of the floating third and fourth regions vary. The voltage variation of the fourth region is read out by the readout transistor. The excess majority carriers stored in the third region flow out therefrom into the other main electrode region of the write transistor and become extinct when it operates as a refresh transistor.

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Patent Owner(s)

Patent OwnerAddress
SEMICONDUCTOR RESEARCH FOUNDATIONSENDAI

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nishizawa, Jun-ichi Sendai, JP 152 3265
Tadahiro, Ohmi Sendai, JP 1 22
Tamamushi, Takashige Sendai, JP 37 601

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