Importance

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Abstract

A chip carrier having a plurality of leads thereon for external interconnection with preferably only one of the leads utilized to provide a source of power to the chip and preferably a single lead utilized as a ground connection. The power and ground leads are connected to an interdigitated lead array at the center of the chip carrier with the chip being secured to the chip carrier above the interdigitated pattern. The chip is bonded to a dielectric sliver which rests above a glass filler and bonding agent which fills the space between the interdigitated pattern and the sliver. The chip is hermetically sealed within the ceramic cap which is bonded to the chip carrier. Power and ground connections are made, from the chip directly to a pair of buses surrounding the interdigitated pattern rather than to leads extending outwardly to the edge of the chip carrier.

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First Claim