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Abstract

A digital data correlator is provided which detects the presence of a particular sequence, or correlating pattern, of binary data bits in a serial binary data stream, is tolerant of data errors, and is adjustable to accept different numbers of data errors. The correlator includes a shift register of the CMOS type, a plurality of inverters of the CMOS type connected to selected outputs of the register at which bits of a particular logic value are expected for a properly positioned correlating pattern in the register, and a plurality of like-valued resistances coupled to the outputs of the register and to the inverters. Erroneous bits in the register cause an error voltage to be produced at a common node point coupled to the resistances. The value of the error voltage is compared in a comparator against a threshold reference voltage of a value related to an acceptable number of erroneous bits. An output of a first logic value is produced by the comparator when the number of erroneous bits in the register exceeds the acceptable number, and an output of a second logic value is produced by the comparator when the number of erroneous bits in the register is equal to or less than the acceptable number. The digital data correlator further includes circuitry capable of altering the number of erroneous bits that will be tolerated or accepted by the correlator.

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