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Abstract

A clocked storage logic array is formed from a plurality of columns and a plurality of rows disposed orthogonal to the columns. Logic cells interconnect selected columns and rows. At least one storage cell is operatively associated with at least one data column. The storage cell utilizes only two column conductors which are time shared to provide a data path from a memory element in the storage cell to a specified row or rows and back from the row(s) through the same column conductors to the memory. A plurality of phase-displaced clock periods are generated which operate in association with logic cells to cause selected rows to assume binary states determined by the binary state of interconnected columns, and vice-versa. The clock periods also cooperate with storage cells to enable the two column conductors to be time shared.

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