Address decode system
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United States of America Patent
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Nov 29, 1983
Grant Date -
N/A
app pub date -
May 29, 1980
filing date -
May 29, 1980
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An address decode scheme decodes address lines using a minimum number of electrical conductors and minimum area on the chip. Instead of decoding the true and the complementary signals of each address input using a PLA or static gate, the present decode scheme uses two sets of programmable transistors for respectively detecting zeros and ones on the address lines and for generating selected high and low decode signals in conjunction with precharge, discharge, and control transistors. This invention is equally effective in CMOS, NMOS, or PMOS technologies.
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