Main bus interface package
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United States of America Patent
Stats
-
Dec 6, 1983
Grant Date -
N/A
app pub date -
Apr 14, 1980
filing date -
Apr 14, 1980
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In a data processing system having a plurality of units and a priority controller for controlling access to a bus by any of the units, each of the units is provided with a lock register having a stage corresponding to each unit connected to the bus. Each word placed on the bus by a source unit includes a lock bit which, in each unit except the source and destination units, sets the stages of the lock registers corresponding to the source and destination units. When a stage of a lock register is set it prevents the unit in which the register is located from attempting to communicate with a unit whose stage of the lock registers is set. On the last transmission between two units the word placed on the bus has a false lock bit which resets the stages of all of the lock registers corresponding to the source and destination units.
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