Testing semiconductor furnaces for heavy metal contamination

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United States of America Patent

PATENT NO 4420722
SERIAL NO

06206715

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A technique for testing for heavy metal contamination in semiconductor processing furnaces includes use of a chip having a plurality of PN-junctions, at least one of which is completely isolated from the sides of the chip. The chip is manufactured to exhibit a high reverse recovery time and this can be conveniently accomplished by a combination of a gettering layer to getter the heavy metal atoms away from the junction and by never raising the temperature of the chip above 800.degree. C. after the gettering layer is provided. In use, the chip is fed through a furnace either with or, preferably before the wafers being processed, which is operating at the conditions under which semiconductor devices are to be processed. After the chip is removed from the furnace, its reverse recovery time is measured and compared to its initial reverse recovery time to determine if it has decreased.

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Patent Owner(s)

Patent OwnerAddress
INTERSIL CORPORATION2401 PALM BAY ROAD PALM BAY FL 32905

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Todd, Albert A Mountaintop, PA 1 13

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