Memory array with redundant elements
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United States of America Patent
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-
Dec 20, 1983
Grant Date -
N/A
app pub date -
Oct 8, 1981
filing date -
Oct 8, 1981
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory array formed on a single chip is provided with at least one redundant column (or row) of memory cells in addition to 'standard' number of columns and rows where the spare column (or row) of cells is designed to be substituted for a standard column (or row) found to have defective cells. Programmable non-volatile electrically alterable elements are connected to the column (or rows) conductors of the standard and redundant columns (or rows) of cells for selectively disconnecting from the memory circuit a standard column (or rows) containing defective cells and substituting therefor a redundant column (or row) of cells.
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