Method of and system for evaluating bit errors in testing a signal path

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United States of America Patent

PATENT NO 4428076
SERIAL NO

06330719

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Abstract

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In order to evaluate the fidelity of a transmission line or other test object, a pseudorandom bit pattern is fed to the input end of that test object and is compared bit by bit with the pattern exiting at its output end. Since independent transmission errors are considered particularly relevant for this evaluation, in contrast to consequential errors following an initial error within a predetermined number of bit cycles, an error pulse emitted by the bit comparator causes the blocking of further error pulses for a selected time interval. The blocking may be effected by a retriggerable monoflop of adjustable off-normal period or by a presettable down counter.

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Patent Owner(s)

Patent OwnerAddress
WANDEL & GOLTERMANN GMBH & CO KGMUHLEWEG 5 A CORP OF GERMANY D-7412 ENINGEN

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Schuon, Eberhard Eningen, DE 2 36

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