Consecutive addressing of a semiconductor memory
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United States of America Patent
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-
Jan 31, 1984
Grant Date -
N/A
app pub date -
Jul 23, 1981
filing date -
Jul 23, 1980
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A high speed memory device comprises memory cells arrayed in rows and columns, a row decoder for selecting the rows, a column decoder for selecting the columns, a shift register arranged in parallel with the column decoder, and control means for operatively enabling the shift register, in which consecutive access to a plurality of memory cells belonging to the same selected row can be performed from the column address designated by the column decoder.
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