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Abstract

A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The instruction responsive apparatus thereof responds to unique microinstructions which, for example, provide for the selection of one of a plurality of interrupt routines each corresponding to an interrupt request from a different external device, provide for the sequential loading of a plurality of segment identification registers each pointing to selected memory management tables associated with a segment storage region of main memory, provide for a program counter relative jump operation, provide for zero-extending or sign-extending 16-bit words to 32-bit words having the same value, and provide for the multiplication of the lower 16 bits of two 32-bit accumulators and the sign-extension of the 16-bit result to form a 32-bit word.

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First Claim