Interrupt pre-processor with dynamic allocation of priority levels to requests queued in an associative CAM
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United States of America Patent
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Mar 20, 1984
Grant Date -
N/A
app pub date -
Jun 11, 1981
filing date -
Sep 27, 1980
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Interrupt requests of different priorities, presented by various interrupt sources (0 to 3), are transferred through control ST, in an associative storage and selection process, into preprocessing elements PE0 and PE1. These elements are variably assigned by controls ST to receive and preprocess requests of associated priority. The preprocessing generates a starting address of a program routine for servicing the respective request. This address is transferred to a common processor which executes the routine. The preprocessing elements can be structured to rapidly generate a succession of different starting addresses relative to several interrupt requests having the priority assigned to that element.
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