Process for the controlled etching of tapered vias in borosilicate glass dielectrics
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United States of America Patent
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Mar 27, 1984
Grant Date -
N/A
app pub date -
Aug 8, 1983
filing date -
Aug 8, 1983
priority date (Note) -
Expired
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Abstract
A process is disclosed for etching openings in a relatively thick layer of borosilicate glass while controlling the degree of taper of the sidewalls of the opening, the taper being in excess of about 45.degree.. The process involves (1) depositing a layer of silicon nitride that contains silicon in an amount in excess of stoichoimetric in Si.sub.3 N.sub.4, (2) densifying the silicon nitride layer, (3) depositing a layer of resist, (4) exposing and developing the layer of resist to define a desired pattern of openings in the borosilicate glass layer, (5) removing the exposed silicon nitride areas, and (6) subjecting the resultant exposed borosilicate glass surface to an etchant for the glass.
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