Power supply rejection characteristics of CMOS circuits

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United States of America Patent

PATENT NO 4442529
SERIAL NO

06231478

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Abstract

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In a conventional CMOS integrated circuit such as a switched capacitor filter, power supply noise signals are coupled from the substrate to high impedance nodes via various parasitic capacitances. To minimize these noise signals and thereby improve the power supply rejection ratio of the circuit, only N-channel transistors are coupled to the nodes. Additionally, the P-tubs of these transistors are connected to an on-chip regulated power supply. Moreover, for certain metallic runners and capacitors of the circuit that are connected to the specified nodes and parasitically coupled to the substrate, grounded P-tubs are formed directly under the runners and capacitors.

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Patent Owner(s)

Patent OwnerAddress
BELL TELEPHONE LABORATORIES INCORPORATED600 MOUNTAIN AVENUE A CORP OF NY MURRAY HILL NJ 07974-2070

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ahuja, Bhupendra K Sunnyvale, CA 12 382
Dwarakanath, Mirmira R Berkeley Heights, NJ 5 71

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