High-voltage CMOS process
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United States of America Patent
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Apr 17, 1984
Grant Date -
N/A
app pub date -
Feb 1, 1982
filing date -
Feb 1, 1982
priority date (Note) -
Expired
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Importance
Abstract
A high-voltage CMOS process, providing (for 5 micron geometries) both field thresholds and junction breakdowns in excess of 20 volts, wherein only one channel stop implant is used. A double-well process in an epitaxial structure is used. Phosphorus is preferably used as the dopant for the N-tank, and boron is used for the blanket channel stop implant. The boron tends to leach into oxide, and the phosphorus tends to accumulate at the surface, and a high field threshold is achieved over both PMOS and NMOS regions.
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