Memory system for microprocessor with multiplexed address/data bus
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United States of America Patent
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-
Apr 17, 1984
Issued Date -
N/A
app pub date -
Oct 13, 1981
filing date -
Oct 9, 1979
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory system for a digital processor device having a 16-bit bidirectional bus with multiplexed addresses and data employs separate memory devices for the high order and low order data bytes. When less than 64K words of memory are used, there are unused address lines in the bus. A microcomputer may use memory devices partitioned 4K.times.8, needing 12 address pins. Both devices are constructed the same, but one accesses the low order byte and the other the high order byte under control of a single byte-select terminal. Mapping of the bus to memory device connections and internal connection of unused pins to address inputs or data input/output lines within the memory devices, along with the byte-select function, allow a single type of device to function in either position.
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