Byte-wide dynamic RAM with multiplexed internal buses
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United States of America Patent
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May 15, 1984
Grant Date -
N/A
app pub date -
Apr 29, 1982
filing date -
Apr 29, 1982
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An MOS dynamic RAM organized in a byte-wide arrangement is described. An internal bus is used for multiplexed column address signals and data. Other multiplexing reduced the lines associated with the input/output circuits. A unique power-on circuit automatically resets clock generators if they are not operative after power is applied.
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