Importance

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Abstract

A display processor for a raster-display type system comprising a display memory with the capacity of storing at least one page of video information to be displayed over the screen of a cathode-ray tube and a cathode-ray tube (CRT) control circuit which divides the frequency of the externally applied clock pulse to generate the address signal and the vertical and horizontal sync signals, the address signal being applied to the display memory while the vertical and horizontal sync signals are applied to the CRT display device. The present invention further adds a comparator which compares the external vertical synchronizing signal with the internal vertical sync signal and a sync circuit which responds to the output from the comparator to permit or inhibit the passage of the external clock pulse to the CRT control circuit. A plurality of such display processors are used and can be synchronized in operation so that a plurality of pages of video information can be displayed in mutually superimposed relationship on the same face of a cathode-ray tube, whereby versatile displays can be presented.

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First Claim