Importance

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Abstract

A single tester tests both LSI and memory devices by storing test signals and standards for the pins of LSI devices in a storage element, providing test signals and standards for the data pins of memory devices from a generator, and selectably routing the test signals and standards from the storage element for LSI testing and from the generator for memory testing; format and timing information for each test signal and standard (for LSI testing) or for groups of test signals and standards (for memory testing) is stored in a second storage element and addresses corresponding to each test signal and standard (for LSI testing) or to each group of test signals and standards (for memory testing) and selectably provided to the second storage element.

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First Claim