Fabrication of FETs
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United States of America Patent
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-
Jun 12, 1984
Grant Date -
N/A
app pub date -
May 27, 1983
filing date -
May 27, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a layer such as palladium over the gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon and palladium form a silicide which is then selectively etched leaving the remaining polycrystalline silicon aligned with the gate.
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